71. The classification of BUSes into synchronous and asynchronous is based on . . . . . . . .
72. . . . . . . . . is used to reset all the device controls to their startup state.
73. The only draw back of using the early start protocol is . . . . . . . .
74. The Bit extension of the register is denoted with the help of . . . . . . . . symbol.
75. The code sent by the device in vectored interrupt is . . . . . . . . long.
76. Interrupts form an important part of . . . . . . . . systems.
77. The ARM processors don't support Byte addressability.
78. . . . . . . . . register is used for the purpose of controlling the status of each interrupt request in parallel priority interrupt.
79. All instructions in ARM are conditionally executed.
80. For a 3 BUS architecture, is the below code correct for adding three numbers?
PCout, R = B, Marin, READ, Inc PC
WMFC
MDRout, R = B, IRin
R4outa, R5outb, Select A, ADD, R6in, End
PCout, R = B, Marin, READ, Inc PC
WMFC
MDRout, R = B, IRin
R4outa, R5outb, Select A, ADD, R6in, EndRead More Section(Computer Architecture)
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