11. The time delay between two successive initiations of memory operation . . . . . . . .
12. The instruction, Add #45,R1 does . . . . . . . .
13. The DMA transfers are performed by a control circuit called as . . . . . . . .
14. The Sun micro systems processors usually follow . . . . . . . . architecture.
15. The transformation between the Parallel and serial ports is done with the help of . . . . . . . .
16. The higher order bits of the virtual address generated by the processor forms the . . . . . . . .
17. There exists a separate block to increment the PC in multiple BUS organisation.
18. The signal used to initiate device select . . . . . . . .
19. DDR SDRAM's perform faster data transfer by . . . . . . . .
20. The method which offers higher speeds of I/O transfers is . . . . . . . .
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