21.
A 1-bit full adder takes 20 ns to generate carry-out bit and 40 ns for the sum bit. What is the maximum rate of addition per second when four 1-bit full adders are cascaded?

27.
The Boolean expression $$\left( {\overline {\text{A}} + {\text{B}}} \right)\left( {{\text{A}} + \overline {\text{C}} } \right)\left( {\overline {\text{B}} + \overline {\text{C}} } \right)$$     simplifies to

29.
Consider the following statements regarding the Moore and Mealy models:
1. In the Mealy circuit, the final output depends only on the present state of memory elements.
2. In the Moore circuit, output can change in between the clock edges if the external inputs change.
3. The implementation of a logic function in Mealy circuit needs more number of states than Moore circuit.
Which of the above statements are not correct?

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