32.
A 1-to-8 demultiplexer with data input Din, address inputs S0, S1, S2 (with S0 as the LSB) and $${\overline {\text{Y}} _0}$$ to $${\overline {\text{Y}} _7}$$ as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders (with enable input $$\overline {\text{E}} $$ and address inputs A0 and A1) as shown in the figure Din, S0, S1 and S2 are to be connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P, Q, R and S terminals should be
Digital Electronics mcq question image

34.
A single ROM is used to design a combinational circuit described by a truth table. What is the number of address lines in the ROM?

35.
Match List-I (Boolean logic function) with List-II (Inverse of function) and select the correct answer using the options given below the lists:
List-I List-II
a. $${\text{ab}} + {\text{bc}} + {\text{ca}} + {\text{abc}}$$ 1. $$\overline {\text{a}} \left( {\overline {\text{b}} + \overline {\text{c}} } \right)$$
b. $${\text{ab}} + \overline {\text{a}} \overline {\text{b}} $$ 2. $$\overline {\text{a}} \overline {\text{b}} + \overline {\text{b}} \overline {\text{c}} + \overline {\text{a}} \overline {\text{c}} $$
c. $${\text{a}} + {\text{bc}}$$ 3. $$\left( {{\text{a}} \oplus {\text{b}}} \right){\text{c}}$$
d. $$\left( {\overline {\text{a}} + \overline {\text{b}} + \overline {\text{c}} } \right)\left( {{\text{a}} + \overline {\text{b}} + \overline {\text{c}} } \right)\left( {\overline {\text{a}} + \overline {\text{b}} + {\text{c}}} \right)$$ 4. $${\text{abc}} + \overline {\text{a}} {\text{bc}} + {\text{ab}}\overline {\text{c}} $$    

40.
The dual form of (A + B) is:

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