81. A 12-bit ADC is employed to convert an analog voltage of zero to 10 volts. The resolution of the ADC is
82. What is the maximum clock frequency at which following circuit can be operated without timing violations? Assume that the combinational logic delay is 10 ns and the clock duty cycle varies form 40% to 60%
83. A sequential circuit using D Flip-Flop and logic gates is shown in the figure, where X and Y are the inputs and Z is the output. The circuit is
84. The output of the 74 series gate of TTL gates is taken from a BJT in
85. The circuit shown in the figure has 4 boxes each described by inputs P, Q, R and outputs Y, Z with $${\text{Y}} = {\text{P}} \oplus {\text{Q}} \oplus {\text{R,}}\,\,{\text{Z}} = {\text{RQ}} + \overline {\text{P}} {\text{R}} + {\text{Q}}\overline {\text{P}} $$
The circuit acts as a
The circuit acts as a
86. For the gate in the given figure the output will be . . . . . . . .
87. The 54/74164 chip is as 8-bit serial-input-parallel-output shift register. The clock is 1 MHz. The time needed to shift an 8-bit binary number into the chip is
88. For the code X1 = (000, 111) how many errors can be successfully detected?
89. IC 74 HC00 series belong to,
90. In S-R latch, when the SET input is made high, output Q becomes:
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