21. A microcontroller differs from a microprocessor in terms of
22. Consider the following 8085 interrupts:
1. TRAP
2. INTR
3. RST 6
4. RST 7.5
5. RST 0
The software interrupt are
1. TRAP
2. INTR
3. RST 6
4. RST 7.5
5. RST 0
The software interrupt are
23. Match List-I with List-II and select the correct answer using the options given below the lists:
List-I (Pre terminals)
List-II (Applications)
a. SID, SOD
1. Wait state
b. Ready
2. Interrupt
c. TRAP
3. Serial data transfer
d. ALE
4. Memory of I/O read/wire
5. Address latch control
| List-I (Pre terminals) | List-II (Applications) |
| a. SID, SOD | 1. Wait state |
| b. Ready | 2. Interrupt |
| c. TRAP | 3. Serial data transfer |
| d. ALE | 4. Memory of I/O read/wire |
| 5. Address latch control |
24. Define the type of instruction with its addressing mode. (8086 ALP) IN AX, 04H
25. Consider the following 8085 instructions:
MVI A, A9H
MVI B, 57H
ADD B
ORA A
The flag status (S, Z, CY) after the instruction ORA A is executed, is
MVI A, A9H
MVI B, 57H
ADD B
ORA A
The flag status (S, Z, CY) after the instruction ORA A is executed, is
26. Consider the following:
1. Sign Flag
2. Zero Flag
3. Carry Flag
4. Parity Flag
Which of the above flags of 8085 get affected by the instruction SUB B?
1. Sign Flag
2. Zero Flag
3. Carry Flag
4. Parity Flag
Which of the above flags of 8085 get affected by the instruction SUB B?
27. In a microprocessor, when a CPU is interrupted, it
28. Consider the following statements:
The SIM instruction outputs the contents of accumulator to define:
1. Interrupt mask bit.
2. Interrupt pending bit.
3. Serial input data line.
4. Serial output data line.
Which of the statements given above are correct?
The SIM instruction outputs the contents of accumulator to define:
1. Interrupt mask bit.
2. Interrupt pending bit.
3. Serial input data line.
4. Serial output data line.
Which of the statements given above are correct?
29. A microprocessor with 12-bit address bus will be able to access . . . . . . . . kilobytes of memory.
30. Which one of the following interrupts is both level and edge sensitive?
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