The master indicates that the address is loaded onto the BUS, by activating . . . . . . . . signal.

Which of the following is not a component of Von Neumann architecture?

A. CPU

B. ALU

C. Memory Unit

D. I/O Interface

What does SIMD stand for in computer architecture?

A. Single Input Multiple Drive

B. Single Input Multiple Data

C. Single Instruction Multiple Drive

D. Single Instruction Multiple Data

Which cache is typically smaller and faster compared to others in a computer system?

A. L2 Cache

B. L3 Cache

C. L1 Cache

D. Virtual Cache

Which register in the CPU stores the address of the next instruction to be fetched?

A. Instruction Register

B. Program Counter

C. Accumulator

D. None of the above