The pipelined architecture of the 8086 allows the fetch & execute cycles to . . . . . . . . instructions/clock cycle

In one’s complement 8 bit representation 11111111 represents

A. +0

B. -0

C. +1

D. -1

Circuit A is a 1-bit adder; circuit B is a 1 bit multiplier.
[Hint: Construct the truth table for the adder and the multiplier]

A. Circuit A has more gates than circuit B

B. Circuit B has more gates than circuit A

C. Circuit A has the same number of gates as circuit B

D. None of the above

An e-mail message can be sent to many recipients.

A. True

B. False

For the number A[15:0] = 0110110010001111, A[14:13] is ______ A[3:2].

A. Less than

B. Greater than

C. The same as

D. Cannot be determined