All transistor in the N output current mirror in the figure are matched with a finite gain β and early voltage VA = ∞. The expression for load current is
A. $$\frac{{{{\text{I}}_{{\text{ref}}}}}}{{\left( {1 + \frac{{\left( {1 + {\text{N}}} \right)}}{{\beta \left( {\beta + 1} \right)}}} \right)}}$$
B. $$\frac{{{{\text{I}}_{{\text{ref}}}}}}{{\left( {1 + \frac{{\text{N}}}{{\beta \left( {\beta + 1} \right)}}} \right)}}$$
C. $$\frac{{\beta {{\text{I}}_{{\text{ref}}}}}}{{\left( {1 + \frac{{\left( {1 + {\text{N}}} \right)}}{{\beta \left( {\beta + 1} \right)}}} \right)}}$$
D. $$\frac{{\beta {{\text{I}}_{{\text{ref}}}}}}{{\left( {1 + \frac{{\text{N}}}{{\beta \left( {\beta + 1} \right)}}} \right)}}$$
Answer: Option A
This Question Belongs to Electronics And Communications Engineering >> Analog Electronics
The action of JFET in its equivalent circuit can best be represented as a
A. Current controlled Current source
B. Current controlled voltage source
C. Voltage controlled voltage source
D. Voltage controlled current source
In a p+n junction diode under reverse bias, the magnitude of electric field is maximum at
A. The edge of the depletion region on the p-side
B. The edge of the depletion region on the n-side
C. The p+n junction
D. The center of the depletion region on the n-side
To prevent a DC return between source and load, it is necessary to use
A. Resistor between source and load
B. Inductor between source and load
C. Capacitor between source and load
D. Either A or B
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