21. Which one of the following is true with regard to a CPU having a single interrupt request line and single interrupt grant line?
i) Neither vectored nor multiple interrupting devices is possible.
ii) Vectored interrupts is not possible but multiple interrupting devices is possible.
iii) Vectored interrupts is possible and multiple interrupting devices is not possible.
iv) Both vectored and multiple interrupting devices are possible.
i) Neither vectored nor multiple interrupting devices is possible.
ii) Vectored interrupts is not possible but multiple interrupting devices is possible.
iii) Vectored interrupts is possible and multiple interrupting devices is not possible.
iv) Both vectored and multiple interrupting devices are possible.
22. The assembler stores all the names and their corresponding values in . . . . . . . .
23. IOPL stands for . . . . . . . .
24. REPINS instruction is used to . . . . . . . .
25. The controller is connected to the . . . . . . . .
26. Which of the register/s of the processor is/are connected to Memory Bus?
27. Which is fed into the BUS first by the initiator?
28. The side of the interface circuits, that has the data path and the control signals to transfer data between interface and device is . . . . . . . .
29. The PC is incorporated with the help of general purpose registers.
30. If we want to perform memory or arithmetic operations on data in Hexa-decimal mode then we use . . . . . . . . symbol before the operand.
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