41. The method of synchronising the processor with the I/O device in which the device sends a signal when it is ready is?
42. The RAS and CAS signals are provided by the . . . . . . . .
43. . . . . . . . . is used to detect and correct the errors that may occur during data transfers.
44. The less space consideration as lead to the development of . . . . . . . . (for large memories).
45. MRDC stands for . . . . . . . .
46. . . . . . . . . register Connected to the Processor bus is a single-way transfer capable.
47. The disadvantage of the EEPROM is/are . . . . . . . .
48. The higher order bits of the address are used to . . . . . . . .
49. The IA-32 architecture associates different parts of memory called . . . . . . . . with different usages.
50. The bits used to indicate the status of the page in the memory is called . . . . . . . .
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