51. The cache bridges the speed gap between . . . . . . . . and . . . . . . . .
52. We describe a protocol of input device communication below:
i) Each device has a distinct address.
ii) The BUS controller scans each device in a sequence of increasing address value to determine if the entity wishes to communicate
iii) The device ready to communicate leaves its data in the I/O register
iv) The data is picked up and the controller moves to the step a
Identify the form of communication best describes the I/O mode amongst the following.
i) Each device has a distinct address.
ii) The BUS controller scans each device in a sequence of increasing address value to determine if the entity wishes to communicate
iii) The device ready to communicate leaves its data in the I/O register
iv) The data is picked up and the controller moves to the step a
Identify the form of communication best describes the I/O mode amongst the following.
53. DEVSEL# signal is used . . . . . . . .
54. To increase the speed of memory access in pipelining, we make use of . . . . . . . .
55. In a system, which has 32 registers the register id is . . . . . . . . long.
56. If a unit completes its task before the allotted time period, then . . . . . . . .
57. Out of the following which is not a CISC machine.
58. During the execution of the instructions, a copy of the instructions is placed in the . . . . . . . .
59. The word line is driven by the . . . . . . . .
60. The TLB is incorporated as part of the . . . . . . . .
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