71. The Interface circuits generate the appropriate timing signals required by the BUS control scheme.
72. In the output interface of the parallel port, along with the valid signal . . . . . . . . is also sent.
73. The iconic feature of the RISC machine among the following is . . . . . . . .
74. . . . . . . . . provides a separate physical connection to the memory.
75. The Instruction, LDM R10!, {R0,R1,R6,R7} . . . . . . . .
76. A . . . . . . . . gate is used to detect the occurrence of an overflow.
77. The extra time needed to bring the data into memory in case of a miss is called as . . . . . . . .
78. In order to read multiple bytes of a row at the same time, we make use of . . . . . . . .
79. The master indicates that the address is loaded onto the BUS, by activating . . . . . . . . signal.
80. In the memory hierarchy, as the speed of operation increases the memory size also increases.
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