In the circuit shown, the ports Q₁ and Q₂ are in the states Q₁ = 1, Q₂ = 0. The circuit is now subjected to two complete clock pulses. The state of these ports now becomes

The circuit shown above

A. is a common-emitter amplifier

B. uses a p-n-p transistor

C. is an oscillator

D. has a voltage gain less than one

The Boolean expression $$B\left( {A + B} \right) + A\left( {\overline B + A} \right)$$     can be realized using minimum number of

A. 1 AND gate

B. 2 AND gates

C. 1 OR gate

D. 2 OR gates

An amplifier of gain 1000 is made into a feedback amplifier by feeding 9.9% of its output voltage in series with the input opposing. If f_L = 20 Hz and f_H = 200 kHz for the amplifier without feedback, then due to the feedback

A. the gain decreases by 10 times

B. the output resistance increases by 10 times

C. the f_H increases by 100 times

D. the input resistance decreases by 100 times

The following circuit (where, R_L ≫ R) performs the operation of

A. OR gate for a negative logic system

B. NAND gate for a negative logic system

C. AND gate for a positive logic system

D. AND gate for a negative logic system