In the circuit shown, the ports Q₁ and Q₂ are in the states Q₁ = 1, Q₂ = 0. The circuit is now subjected to two complete clock pulses. The state of these ports now becomes

A. is a common-emitter amplifier B. uses a p-n-p transistor C. is an oscillator D. has a voltage gain less than one

A. 1 AND gate B. 2 AND gates C. 1 OR gate D. 2 OR gates

A. the gain decreases by 10 times B. the output resistance increases by 10 times C. the f_H increases by 100 times D. the input resistance decreases by 100 times

A. OR gate for a negative logic system B. NAND gate for a negative logic system C. AND gate for a positive logic system D. AND gate for a negative logic system