The drain gate capacitance of a junction FET is 2 pF. Assuming a common source voltage gain of 20. What is the input capacitance due to Miller effect?

The action of JFET in its equivalent circuit can best be represented as a

A. Current controlled Current source

B. Current controlled voltage source

C. Voltage controlled voltage source

D. Voltage controlled current source

In a CB amplifier the maximum efficiency could be

A. 99%

B. 85%

C. 50%

D. 25%

In a p⁺n junction diode under reverse bias, the magnitude of electric field is maximum at

A. The edge of the depletion region on the p-side

B. The edge of the depletion region on the n-side

C. The p⁺n junction

D. The center of the depletion region on the n-side

To prevent a DC return between source and load, it is necessary to use

A. Resistor between source and load

B. Inductor between source and load

C. Capacitor between source and load

D. Either A or B