A 4-line-to-1-line multiplexer shown in figure-I (the same as per IEEE convention is shown in figure-II) is fed with three logic inputs A, B and C as shown. The output of the multiplexer will be

A. ∑m(0, 1, 2, 4)

B. ∑m(0, 3, 5, 7)

C. ∑m(3, 5, 6, 7)

D. ∑m(1, 2, 5, 6)

Answer: Option C