A standard CMOS inverter is designed with equal rise and fall times (βn = βp). If the width of the PMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin (NML) and the HIGH noise margin NMH ?
A. NML decreases and NMH increases
B. No change in the noise margins
C. Both NML and NMH increase
D. NML increases and NMH decreases
Answer: Option D
This Question Belongs to Electronics And Communications Engineering >> Digital Electronics
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