Consider the logic circuit with input signal TEST shown in the figure. All gates in the figure shown have identical non-zero delay. The signal TEST which was at logic LOW is switched to logic HIGH and maintained at logic HIGH. The output:
A. Stays LOW throughout
B. Pulses from LOW to High to LOW
C. Stays HIGH throughout
D. Pulses from HIGH to LOW to HIGH
Answer: Option D
This Question Belongs to Electronics And Communications Engineering >> Digital Electronics
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