For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero.
If the clock (Clk) frequency is 1 GHz, then the counter behaves as a
A. mod-5 counter
B. mod-6 counter
C. mod-7 counter
D. mod-8 counter
Answer: Option D
This Question Belongs to Electronics And Communications Engineering >> Digital Electronics
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