Which one of the following statements is correct?

A. In serial adder, if d and D, respectively, are the full adder and flip-flop delay, then the time required to perform n bit addition is [n(d + D)]

B. Maximum delay in n bit parallel adder is 'nd', where d is delay of full adder

C. If d is the delay of two-level circuit, then the total delay of a carry look ahead adder is only 3d

D. Delay of D flip flop is always less than T flip-flop

Answer: Option B