A 1-to-8 demultiplexer with data input D_in, address inputs S₀, S₁, S₂ (with S₀ as the LSB) and $${\overline {\text{Y}} _0}$$ to $${\overline {\text{Y}} _7}$$ as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders (with enable input $$\overline {\text{E}} $$ and address inputs A₀ and A₁) as shown in the figure D_in, S₀, S₁ and S₂ are to be connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P, Q, R and S terminals should be