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This question belongs to Electronics And Communications Engineering Digital Electronics

Digital Electronics

?

A standard CMOS inverter is designed with equal rise and fall times (β_n = β_p). If the width of the PMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin (NM_L) and the HIGH noise margin NM_H ?

A) NM_L decreases and NM_H increases B) No change in the noise margins C) Both NM_L and NM_H increase D) NM_L increases and NM_H decreases

Answer & Solution

Correct Answer: Option D

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