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In a 3-input CMOS NAND gate the substrate terminals of NMOS...

This question belongs to Electronics And Communications Engineering Digital Electronics
Digital Electronics
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In a 3-input CMOS NAND gate, the substrate terminals of NMOS transistors are grounded (lowest potential available in the circuit) and the substrate terminals of PMOS transistors are connected to VDD (maximum positive potential in the circuit). Which of the following transistors may suffer in this circuit from body bias effect?

Answer & Solution
Correct Answer: Option A
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