Two D-flip-flops, as shown below, are to be connected as a synchronous counter that goes through the following Q1Q0 sequence 00 → 01 → 11 → 10 → 00 → . . . . . The inputs D0 and D1 respectively should be connected as

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Digital Electronics

Two D-flip-flops, as shown below, are to be connected as a synchronous counter that goes through the following Q₁Q₀ sequence
00 → 01 → 11 → 10 → 00 → . . . . .
The inputs D₀ and D₁ respectively should be connected as

A) $${\overline {\text{Q}} _1}{\text{ and }}{{\text{Q}}_0}$$ B) $${\overline {\text{Q}} _0}{\text{ and }}{{\text{Q}}_1}$$ C) $${\overline {\text{Q}} _1}{{\text{Q}}_0}{\text{ and }}{\overline {\text{Q}} _1}{{\text{Q}}_0}$$ D) $${\overline {\text{Q}} _1}{\overline {\text{Q}} _0}{\text{ and }}{{\text{Q}}_1}{{\text{Q}}_0}$$

Answer & Solution

Correct Answer: Option A

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