Digital Electronics MCQ Questions & Answers | ECE

The logic operations of two combinational circuits given in Figure-I and Figure-II are

A 1-to-8 demultiplexer with data input D_in, address inputs S₀, S₁, S₂ (with S₀ as the LSB) and $${\overline {\text{Y}} _0}$$ to $${\overline {\text{Y}} _7}$$ as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders (with enable input $$\overline {\text{E}} $$ and address inputs A₀ and A₁) as shown in the figure D_in, S₀, S₁ and S₂ are to be connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P, Q, R and S terminals should be

How many AND, OR and EXOR gates are required for the configuration of full adder?

A single ROM is used to design a combinational circuit described by a truth table. What is the number of address lines in the ROM?

Match List-I (Boolean logic function) with List-II (Inverse of function) and select the correct answer using the options given below the lists:

List-I	List-II
a. $${\text{ab}} + {\text{bc}} + {\text{ca}} + {\text{abc}}$$	1. $$\overline {\text{a}} \left( {\overline {\text{b}} + \overline {\text{c}} } \right)$$
b. $${\text{ab}} + \overline {\text{a}} \overline {\text{b}} $$	2. $$\overline {\text{a}} \overline {\text{b}} + \overline {\text{b}} \overline {\text{c}} + \overline {\text{a}} \overline {\text{c}} $$
c. $${\text{a}} + {\text{bc}}$$	3. $$\left( {{\text{a}} \oplus {\text{b}}} \right){\text{c}}$$
d. $$\left( {\overline {\text{a}} + \overline {\text{b}} + \overline {\text{c}} } \right)\left( {{\text{a}} + \overline {\text{b}} + \overline {\text{c}} } \right)\left( {\overline {\text{a}} + \overline {\text{b}} + {\text{c}}} \right)$$	4. $${\text{abc}} + \overline {\text{a}} {\text{bc}} + {\text{ab}}\overline {\text{c}} $$

In Boolean Algebra, AB + AB' is equivalent to

One hexa-decimal digit is sometimes referred to as:

An OR gate may be imagined as

The range of signed decimal numbers that can be represented by 6-bit 1's complement number is

The dual form of (A + B) is: